EDN

Wafer-Level Packaging Reduces Cost, Spurs Recovery

With the industry recovery coming on slowly, cost is a more important factor than ever. Semiconductor manufacturers are constantly under pressure to reduce costs, and during a down cycle they must do ...
Nasdaq

ACM Research Highlights Availability of Portfolio of Wafer-Level Packaging Processing Equipment for OSAT Customers

Extensive Array of Back-End and Advanced Packaging Wet Wafer Process Equipment Leverages ACM’s Experience to Address Emerging Requirements for Wafer-Level Packaging FREMONT, Calif., Oct. 15, 2020 ...
Nasdaq

ACM Research Launches Its First Plating Tool to Support Wafer-Level Packaging and Plating Applications in Compound Semiconductor Manufacturing

FREMONT, Calif., Aug. 25, 2021 (GLOBE NEWSWIRE) -- ACM Research, Inc. (ACM) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging (WLP) ...
EDN

STATS expands wafer-level packaging output

SAN JOSE, Calif. — Citing renewed demand, Singapore's STATS ChipPAC Ltd. is expanding its capacity for wafer-level packaging. STATS ChipPAC has been on a production ramp with wafer-level packaging ...
Semiconductor Engineering

Panel-Level Packaging’s Second Wave Meets Engineering Reality

Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down.
Seeking Alpha

ACM Research Receives Orders for Wafer-Level Packaging Tools from U.S. Customer and R&D Center

FREMONT, Calif., Sept. 04, 2024 (GLOBE NEWSWIRE) -- ACM Research, Inc. (ACMR) (“ACM”) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level ...
Semiconductor Engineering

One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging Using a Photosensitive Dielectric Material

This study investigates creation of 1.0µm RDL structures by a damascene process utilizing a photosensitive permanent dielectric material. The advantage of the photosensitive dielectric approach is ...
Digi Times

Samsung steps up fan-out wafer-level packaging deployment

Samsung Electronics has stepped up its deployment in the fan-out (FO) wafer-level packaging segment with plans to set up related production lines in Japan, according to industry sources. Samsung has ...
Digi Times

South Korea initiates major R&D project to boost chips packaging competitiveness

Recognizing the strategic importance of semiconductor packaging technology, the South Korean government is reportedly initiating a major packaging technology R&D project aimed at assisting companies ...
AZOM

Maximize Performance and Optimizes Costs with Plasma Treatment

Nordson MARCH Addresses the Ways Plasma Treatment during Fan-out Wafer and Fan-out Panel-Level Semiconductor Packaging Maximizes Performance and Optimizes Costs In recent years, there has been an ...
Electronic Design

Thanks To TSVs, 3D IC Packaging Gets Set To Tackle Tough Challenges

Fig 1. The system-in-package approach is part of the trend toward thinner and more integrated 3D IC packages for CPUs, GPUs, and FPGAs for use in camera modules and wireless products, where high ...