IEEE

Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V

Abstract: RISC-V is a promising open-source architecture that targets low-power embedded devices and system-on-chips (SoCs). However, there is a dearth of practical and low-overhead security solutions ...
GitHub

RISC-V Instruction Set Manual

This repository contains the source files for the RISC-V Instruction Set Manual, which consists of the Unprivileged and Privileged volumes. The preface of each document indicates the version of each ...
theregister

Alibaba delivers RISC-V server chip optimized to run China’s top AI models

Alibaba has revealed a new server chip that it says is the most powerful processor ever to use the RISC-V instruction set. According to a social media post by Alibaba’s DAMO Academy, which develops ...
IEEE

A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms

Abstract: In recent years, public-key cryptography has become a fundamental component of digital infrastructures. Such a scenario has to face a new and increasing threat, represented by quantum ...
GitHub

RARS -- RISC-V Assembler and Runtime Simulator

RARS, the RISC-V Assembler, Simulator, and Runtime, will assemble and simulate the execution of RISC-V assembly language programs. Its primary goal is to be an effective development environment for ...