Hackaday

RTL-SDR: Seven Years Later

Before swearing my fealty to the Jolly Wrencher, I wrote for several other sites, creating more or less the same sort of content I do now. In fact, the topical overlap was enough that occasionally ...
Design-Reuse

IP Verification : RTL prototyping: a hardware/software co-verification solution

Traditional ASIC and IP verification methods cannot adequately exercise the hardware and software components of today's designs. This is due to tool performance limitations, which impose a bottleneck ...
EDN

Compiler abstracts RTL for software development

Santa Cruz, Calif. – EDA startup Carbon Design Systems Inc. will open a new approach to presilicon system validation with the launch of its SpeedCompiler and DesignPlayer tools in December. The tools ...
Design-Reuse

Blue Pearl Software Streamlines RTL Verification for Xilinx All Programmable FPGAs and SoCs

SANTA CLARA, California, Jul. 25, 2017 – Blue Pearl Software, Inc., the leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced Visual Verification Suite ...
EDN

Software increases RTL design productivity

The Cadence Joules RTL Design Studio allows front-end engineers to accelerate and improve register transfer level (RTL) design and implementation. By providing access to the physical information ...